10.1 Notes on CACHE Instruction Operations
CH Bit
The CH bit is supported in the R10000 processor. It is modified by a Hit Invalidate (S) or Hit WriteBack Invalidate (S) CACHE instruction. CH is set if there is a hit in the secondary cache, and cleared if there is a miss. The CH bit can also be modified by a MTC0 instruction.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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